One core, both codecs: how resource sharing, a 4-lane CTU engine and end-to-end power engineering hit 4K30 in ~4.3 mm² of logic.
01
One core encodes H.264 (AVC) and H.265 (HEVC) through a unified transform unit and a shared CABAC/CAVLC entropy engine — 70% of entropy logic common across codecs. Measured at 12.8M NAND2-eq gates — ~4.3 mm² of logic at 22nm for the 4-lane VE-2030.
02
Four WPP-parallel lanes sustain 4K30 (VE-2030); the 8-lane VE-2060 reaches 4K60 at the same clock — throughput scales by lanes, not frequency. Lane power-gating drops to one lane at lower tiers. A 12-stage pipeline holds 165-cycle max latency per CTU, with per-lane clock gating worth 25–50% of active power.
03
Hierarchical clock gating, operand isolation across all 12 stages, IEEE 1801 power intent, and 22nm FDSOI body biasing with DVFS and per-lane switched rails — ~40 mW at 1080p60 and ~115 mW at 4K30 HEVC (0.65 V + RBB), down to 2 mW in deep sleep.
04
Byte-exact (cmp = 0) against the JM and HM reference decoders across QP 22–42, both codecs and both bit depths — intra and P-frames including sub-pel motion. 28 self-checking unit tests, plus UVM and constrained-random environments on Verilator. The expensive half of an encoder project, already done.
01
Input stream enters the front-end FIFO and is parsed into macroblocks.
02
Transform & quantization stages feed the entropy coder.
03
Intra reconstruction loop rebuilds reference samples.
04
Bitstream packetizer emits the final NAL units downstream.
The power & area whitepaper and datasheet: per-resolution power tables, area breakdown by subsystem, DVFS operating points, coverage summary and the disclosed-gaps list. Distributed under NDA — see the boilerplate mutual NDA.